Exploiting Parallelism in Cache Coherency Protocol Engines
Abstract
Shared memory multiprocessors are based on memory models, which are precise contracts between hard- and software that spell out the semantics of memory operations. Scalable systems implementing such memory models rely on cache coherency protocols that use dedicated hardware. This paper discusses the design space for high perfor- mance cache coherency controllers and describes the architecture of the programmable protocol engines that were developed for the S3.mp shared memory multiproces- sor. S3.mp uses two independent protocol engines, each of which can maintain multiple, concurrent contexts so that maintaining memory consistency does not limit the system performance. Programmability of these engines allows support of multiple memory organizations, including CC-NUMA and S-COMA.
BibTeX
@conference{Nowatzyk-1995-13962,author = {Andreas Nowatzyk and G. Aybay and M. Browne and E. Kelly and M. Parkin and W. Radke and S. Vishin},
title = {Exploiting Parallelism in Cache Coherency Protocol Engines},
booktitle = {Proceedings of European Conference on Parallel Processing (EURO-PAR '95)},
year = {1995},
month = {August},
pages = {267 - 286},
}