An 800 Mbps multi-channel CMOS serial link with 3x oversampling
Conference Paper, Proceedings of IEEE Custom Integrated Circuits Conference (CICC '95), pp. 451 - 455, May, 1995
Abstract
A CMOS serial link is described that uses a digital PLL with 3x oversampling to recover both clock and data. An implementation with 0.6 um CMOS technology exhibits 800 Mbps operation with BER of less than 10E-12 for pseudo random number sequence. Chip area and power dissipation per channel at 800 Mbps are 2.1 mm x 0.1 mm and 0.75 W, respectively
BibTeX
@conference{Kim-1995-13891,author = {Sungjoon Kim and Kyeongho Lee and Deog-Kyoon Jeong and D. D. Lee and Andreas Nowatzyk},
title = {An 800 Mbps multi-channel CMOS serial link with 3x oversampling},
booktitle = {Proceedings of IEEE Custom Integrated Circuits Conference (CICC '95)},
year = {1995},
month = {May},
pages = {451 - 455},
}
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