Missing the Memory Wall: The Case for Processor/Memory Integration

Abstract

Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-centric designs invest a lot of power and chip area to bridge the widening gap between CPU and main memory speeds. Yet, many large applications do not operate well on these systems and are limited by the memory subsystem performance. This paper argues for an integrated system approach that uses less power-full CPUs that are tightly integrated with advanced memory technologies to build competitive systems with greatly reduced cost and complexity. Based on a design study using the next generation 0.25?, 256Mbit DRAM process and on the analysis of existing machines, it is shownthat processor memory integration can be used to build competitive, scalable and cost-effective MP systems. The results from execution driven uni- and multi-processor simulations are presented that show that the benefits of lower latency and higher bandwidth outweight the restrictions on the size and complexity of the integrated processor. In this system, small direct mapped instruction caches with long lines are very effective, as are column buffer data caches augumented with a victim cache.